Modeling Logical Error Rates in Surface-Code Quantum Computing based on Lattice Surgery and Applications

Abstract

Utility-scale quantum computation requires choosing fault-tolerant error-correcting codes and logical operations in a manner that guarantees a target program execution accuracy. In surface-code-based quantum computers, this requirement translates into the ability to predict the logical error rates of all lattice-surgery operations executed during computation. These logical error rates determine the required code distances, circuit depth, physical-qubit overhead, and, ultimately, the feasibility of large-scale quantum algorithms. In this thesis, we develop an operational benchmarking framework for predicting the logical error rates of surface-code primitives under realistic circuit-level hardware noise. The framework is based on numerical evaluation of experimentally implementable protocols, including single-patch logical memory and two-patch lattice-surgery protocols such as logical teleportation. Rather than attempting to simulate full fault-tolerant algorithms–which is computationally intractable–we extract geometric error scaling models that relate logical failure probabilities to the space–time structure of each protocol and to underlying physical noise parameters. Using these models, we quantify how improvements in hardware performance translate into enhanced logical error suppression and identify the dominant mechanisms limiting fault-tolerant performance. The resulting logical error models are compact, reusable, and directly applicable to resource estimation and architecture-level studies. Together, these results provide a practical bridge between low-level hardware characteristics and high-level fault-tolerant quantum computation, enabling more informed design and evaluation of surface code-based quantum computing architectures.