Predictable Cache Subsystem Design for Real-time Multicores

dc.contributor.authorWang, Xinzhe
dc.date.accessioned2024-08-23T14:29:47Z
dc.date.available2024-08-23T14:29:47Z
dc.date.issued2024-08-23
dc.date.submitted2024-08-12
dc.description.abstractThis thesis focuses on the design of the cache subsystem for multicore real-time systems. Specifically, it looks at the two common contention sources in the cache subsystem that undermine the system's timing predictability: temporal contention (queuing delays resulting from simultaneous shared resource accesses) and spatial contention (conflicts in cache line allocations). Accordingly, this thesis proposes two solutions to address the two problems. First, to address temporal contention induced by the shared last-level cache (LLC), we propose PECC, a predictable exclusive cache coherence mechanism. Unlike the common choice of inclusive cache hierarchies, PECC incorporates an exclusive LLC free of back invalidation, which is a significant contributor to the per-request worst-case latency (PR-WCL) in inclusive hierarchies. As a result, PECC reduces the bound of PR-WCL by 6% and improves the average performance by 2.33 times over the predictable solution with an inclusive LLC. Second, to address spatial contention in the shared LLC, we propose ParRP, a novel cache partitioning scheme that provides cache space isolation for shared data. Conventionally, achieving cache space isolation for shared data is challenging due to its intrinsic sharing nature, which violates the resource isolation principle. ParRP overcomes this by partitioning the replacement policy instead of cache entries. Consequently, ParRP guarantees isolation property even with shared data, enabling isolated worst-case execution time (WCET) analysis without interference from other cores. Our evaluation shows that this leads to a 2.4 times reduction in the WCET of multi-threaded tasks with shared data at the cost of a 16.5% decrease in average performance.
dc.identifier.urihttps://hdl.handle.net/10012/20865
dc.language.isoen
dc.pendingfalse
dc.publisherUniversity of Waterlooen
dc.titlePredictable Cache Subsystem Design for Real-time Multicores
dc.typeMaster Thesis
uws-etd.degreeMaster of Applied Science
uws-etd.degree.departmentElectrical and Computer Engineering
uws-etd.degree.disciplineElectrical and Computer Engineering
uws-etd.degree.grantorUniversity of Waterlooen
uws-etd.embargo.terms0
uws.contributor.advisorPatel, Hiren
uws.contributor.advisorRodolfo, Pellizzoni
uws.contributor.affiliation1Faculty of Engineering
uws.peerReviewStatusUnrevieweden
uws.published.cityWaterlooen
uws.published.countryCanadaen
uws.published.provinceOntarioen
uws.scholarLevelGraduateen
uws.typeOfResourceTexten

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